1. Field of the invention
The field of the invention is that of switch mode power supplies and in particular a zero voltage switching cell using a pulsed current source including a saturable inductor.
2. Description of the prior art
FIG. 1 shows a conventional half-bridge switch mode power supply. A switch mode power supply of this kind is described in "Lea alimentations a frequence de decoupage elevee" ("High switching frequency power supplies") by Daniel SADARNAC, ESE 9, Editions Eyrolles, 1993, part of the "Direction des Etudes et Recherches d'Electricite de France" series.
A voltage source supplies a direct current voltage E to a bridge arm including two switching cells 10, 11 in series. The switching cell 10 includes, connected in parallel, switching means T1, a protection diode D1 and a capacitor C1; the switching cell 11 includes, also connected in parallel, switching means T2, a protection diode D2 and a capacitor C2. The capacitors C1 and C2 may be incorporated into the switching means T1 and T2 rather than added externally. The mid-point P of the bridge arm shown is connected to an inductor cell 1 followed by a load which in this instance is a transformer having a primary winding L2 and a secondary winding L3. A capacitor C3 is connected in parallel with the primary winding L2. The other end of the load constituted by the inductor L2 is connected between two capacitors C4 and C5 to which the DC voltage E is applied.
In the secondary circuit of the transformer, two rectifier diodes D3 and D4 cooperate with two inductors LS and a smoothing capacitor CS to provide a DC output voltage VS applied to a load.
The operation of this power supply is described with reference to FIG. 2 which shows four correlated timing diagrams A through D of signals shown in FIG. 1.
The switching means T1 and T2 are power MOSFET, for example, incorporating the protection diodes D1 and D2. A control circuit (not shown) applies to the gates of the transistors T1 and T2 the control pulse is shown in timing diagrams A and B. These pulses have a period T and a relative time offset in order to turn the transistors T1 and T2 on (saturated) and off (cut off) alternately. When a pulse is applied to the gate of one of the transistors, that transistor is turned on. A pulse is applied to the transistor T1 at time t1, at which time the transistor T2 is turned off. The voltage e (timing diagram C) measured between the common point of the capacitors C4 and C5 and the mid-point of the bridge arm is equal to +E/2, which is the voltage across the capacitor C4. The current j (timing diagram D) flowing through the transistor T1 increases and is supplied to the load consisting of the inductor L1 and the transformer primary (inductor L2). The transistor T1 is turned off at time t2 and the inductor L1 opposes fast variations in the current, which causes the capacitor C1 to be charged and the capacitor C2 to be discharged. The voltage e then falls to --E/2 at time t3, whereupon the diode D2 begins to conduct. The capacitor C2 has a low voltage across it at this time. A guard time dt is provided between the end of conduction in one transistor and the start of conduction in the other transistor, to prevent sudden charging and discharging of the capacitors C1 and C2. This reduces losses. When the voltage e has become negative, the current j is reversed and, at time t4, the transistor T2 is turned on in its turn. The phenomenon is then reproduced symmetrically.
This generates a symmetrical AC voltage e producing an output voltage VS that is dependent on the switching period T.
The capacitance value of the capacitors C1 and C2 represents a compromise between losses and switching frequency. If the capacitance value is high, switching losses are reduced but the switching frequency must be relatively low since more time is required to charge and discharge them. On the other hand, their presence is essential to switching at a low voltage, preferably at zero voltage, which is sometimes called "soft switching".
A known disadvantage of this type of switch mode power supply is that it is essential to use the inductor L1 to enable charging and discharging of the capacitors C1 and C2. If the load is a transformer, its primary inductance is too low to generate sufficient capacitor charging and discharging current. At the times the capacitors are charged and discharged, the current j must be high to enable fast charging and discharging. Accordingly, referring to FIG. 2, the current j has to be sufficiently high during the time periods from t2 to t3 and from t5 to t6, it is also high the rest of the time, during which it flows in the transistors T1 or T2 or in the diodes D1 or D2, which causes conduction losses and switching losses. It is then necessary to overspecify the transistors.
Moreover, if the impedance of the load supplied with power by this device decreases, the current j must nevertheless be present and sufficiently high at the switching times. Losses are therefore high in the absence of the load.
Another problem due to the inductor L1 is that it is difficult to construct and is subject to high iron losses. It must be toroidal for reasons of electromagnetic radiation and, to prevent it overheating, it must be overspecified, leading to problems of overall size. In high current applications, for example, for a 500 W switch mode power supply L1 must have an inductance in the order of a few .mu.H and must be able to withstand a current of 15 A. The presence of this inductor reduces efficiency by an amount in the order of 3%. As the iron losses increase in accordance with an approximate f.sup.2 law, there is also an upper limit on the switching frequency, which must remain below 1 MHz.
In the case of supplying power to a varying load, or if the voltage E is not fixed, the output voltage VS can be maintained constant only by varying the switching frequency. This increases overall size and cost and introduces electromagnetic radiation problems.
A known solution to these problems is described in U.S. patent application Ser. No. 08/397,773 filed 2nd Mar. 1995, the content of which is hereby incorporated by reference. In the above document, the pulsed current source is an LC type circuit in which the current flowing lags by .pi./2 relative to the voltage applied to the load, in order to deliver current pulses for alternately charging and discharging each of the capacitors C1 and C2 on the edges of the AC voltage.
FIG. 3 shows one embodiment of a switch mode power supply using this pulsed current source.
The mid-point P of the bridge arm is connected to a pulsed current source 30 comprising an LC type circuit, i.e. a circuit comprising inductors and capacitors, the circuit being specified so that the current flowing in the circuit lags by .pi./2 relative to the voltage applied to the load 31. The pulsed current source 30 is designed to deliver current pulses for alternately charging and discharging each of the capacitors C1 and C2 on the edges of the AC voltage e. In this example the pulsed current source 30 is connected in parallel with the switching cell 11. It could equally well be connected in parallel with the switching cell 10, as shown in dashed outline. It is also possible to provide a pulsed current source for each switching cell.
Timing diagram D in FIG. 4 shows the trend of the current j supplied by the current source 30, the other timing diagrams (A through C) being identical to those from FIG. 2. The function of the source 30 is therefore to generate a current pulse at the times the switching means open. The current pulses are centered on the rising and falling edges of the voltage e. The current pulses are positive when the voltage e is falling and negative when the voltage e is rising.
The use of an LC type circuit as recommended in the above prior art solution nevertheless requires a considerable amount of wiring if the pulsed current source is a set of LC cells in parallel, and requires precision that increases in proportion to the number of LC cells. Moreover, the overall size, and likewise the cost, are not negligible since a plurality of LC cells are connected in parallel.
Another solution to the problems mentioned above is described in the article "A generic soft switching converter topology with a parallel non-linear network for high power application" by J. A. Ferreira, A. van Ross and J. D. van Wyk, 21st Annual IEEE Power Electronics Specialists Conference, PESC'90 Record, pages 298-304, and also in the article "Pseudo-resonant full bridge DC/DC converter" by O. D. Patterson and D. M. Divan, 18th Annual IEEE Power Electronics Specialists Conference, PESC'87 Record, pages 424-430. This solution consists in providing the pulsed current source in the form of a circuit including a saturable inductor.
FIG. 5 shows a pulsed current source 50 of this kind. A saturable inductor L4 is connected in parallel with a capacitor C6. The pulsed current source 50 can be connected to switching units of the kind used in the source 30 in FIG. 3. The permeability of the inductor L4 decreases as the current applied to it increases and this provides a component having a very low impedance for high currents. In this example the capacitor C6 exercises the function of the capacitors connected to the switching means.
The problem with a current source of the above kind is that iron losses are very high since the current variation traces all of the characteristic B=f(H), where B is the magnetic flux density and H is the magnetic field. To be more precise, the iron losses increase with the flux density B in accordance with an approximate square law. Moreover, the saturation level of an inductor of this kind varies with temperature and from one kind of ferrite (the material routinely used for its manufacture) to another. These various parameter spreads make an inductor of this kind unsuitable for mass-produced switch mode power supplies.
One object of the present invention is to remedy the above drawbacks.
To be more precise, one object of the invention is to provide a switch mode power supply using a low-loss saturable inductor.